İndirgenmiş komut kümeli makina yapılarının incelenmesi

Abstract

ÖZET Yüksek seviyeli dillerdeki uygulamalara yönelik tasar lanan, yüksek performanslı, basit yapılı ve az sayıda komut içeren işlemciler İndirgenmiş Komut Kümeli İşlemciler (Re duced Instruction Set Computer s -RI SC) olarak tanımlanmak tadır. Bu türdeki işlemciler aşağıdaki ortak özellikleri taşı mak tadı r 1 ar. 1-Tek saat çevriminde yürütülen komutlar. 2-Az sayıda adresleme modu. 3-Basi t komut f ormatı. 4-Basit YÜKLE, SAKLA komutları ile bellek erişimi. 5-Çok sayıda genel amaçlı kaydedici. 6-Optimize derleyicilere gereksinim. Basit yapıları dol ayı sı ile RISC işlemcilerin tasa rımları ve ger ç eklenmeler i kolaydır. Bu tezde. Karmaşık Komut Kümeli İşlemci CComplex Instruction Set Computer -CISC) mi mar i yapısının dezavantaj ları ve bu dezavantajları ortadan kaldıran RISC mimari yapısı genel olarak incelenmiştir. Bu mimari yapıdaki geniş kaydedici kimelerinin kullanılma şekilleri, pencere yapısının kullanılması durumunda en etkin pencere yapısı nın saptanması anlatılmıştır. Sabit uzunluklu pencere yapılarında, üstten ve alttan taşma istisnai durumlarında yürütülme süresinde en az artışa sebep olan çerçeve transfer yöntemi tanıtılmıştır. Sabit uzunluklu pencere yapısı kullanan işlemcilere örnek olarak RISC I ve RISC II işlem cileri tanıtılmıştır. Tezde ayrıca, komut bant genişliği ni yonga içi komut cep belleği oluşturarak azaltan MIPS-X ve günümüz genel amaçlı RISC işlemcilerinden olan Am 29000 mimari yapıları incelenmiştir. (vi)

SUMMARY INVESTIGATION OF THE RISC ARCHITECTURE Manufacturers of computers traditionally meet the demand for greater performance by increasing the complexity of their machines. Some vendors have resorted to more complex instructions to bring instruction set up to the level of the desired programing language, while others have added coprocessors and other hardware. Examples of computers whose most recent iterations show substantially increased complexity in comparison with earlier architectures include IBM System/38, the DEC VAX-11 and the Intel iAPX 432. But increased com lex i ty makes the processor harder to design and harder to build especially in VLSI; designs where the nummber of transistors that can be formed are limited. Also, the increased complexity in the control section of the processor increases the decode time of all instruction. The RISC approach: A traditional complex instruction set computer (CISC) relies on hundreds of specialized instructions, dozen of addressing modes, and several high-level languages implemented in hardware. In such a computer, the compiler must consider' 'the many possibilities inherent in a complex instruction and perform a number of memory transfers to execute it. This requires identifying the ideal addressing mode and the shortest instruction format to add the operands in memory. Yet only a small number of instruction types takes up most of a computer's execution time. Loads, call, and branch instructions are found in compiled code more often then any other instruction type. Loads of a constant, loads from memory, calls, and branches occupy from 60 to 80 percent of the CPU's time, and their execution takes longer than many other instruction types. These complex operations can be executed faster by breaking each one down into a series of simple instructions that move data between registers and memory. This is the principle behind the RISC approach.Having almost all instructions perform only basic ALU and shift functions effectively implements the complex instructions found in a CISC as in-line code or as subroutines in a RISC. Some salient characteristics of a RISC-based machine are register to register operations that allow optimization of compilers through reuse of operands with instruction formats, and addressing modes that permit instructions to be decoded in a single machine cycle. Memory-reference instructions, consisting of load and store operations, are also typical. Because the small instruction set {typically containing 30 to 50 instruction types) deals only with operations for memory load and store, a RISC performs all other operations register-to-register thereby reducing memory-addressing overhead. Since the RISC register to register instructions are usually faster than memory accesses, operating speed is increased. Table 1 lists the instruction set of the Berkeley RISC II computer. Table 1 Instruction Set of RISC II (Vİİİ5In some RISC architectures, the register file is organized as a stack of dynamically allocated register sets» or `windows`, with different procedures assigned to separate register sets. To avoid copying parameters from one window to another on each call, the sets are overlapped. In Figure 1. two overlapped register windows are shown. High-order registers of the calling WINDOW A WINDOW A + 1 Figure 1 Ower lapping register windows. program correspond to the low-order registers of the called program. The calling procedure uses these registers to pass the actual parameters, while the called procedure uses them to return the procedure results. This structure is aimed at avoiding the heavy time penalties associated with passing parameters in memory. There are, however, inherent weaknesses in such a structure. In multitasking aplications, there is a heavy context-switching time penalty because the entire register stack must be flushed and reloaded when the processor begins executing another task. There is also a significant degree of inefficiency because a large number of registers are required but only a small fraction are actually in use at any time. In addition, accessing the stack with a sliding window means that variables below the window can only be accessed after the register stack is pushed into memory. Originally, the window approach compensated for shortcomings in compilers since register allocation poses a difficult problem. Compilers, however, now allocate registers more accurately and handle sving and restoring routines more efficiently. Optimizing compilers make maximum use of fewer registers, allowing them to surpass the performance of a massive register-set stack, in terms of both their speed and (ix>their efficiency. Studies from Stanford University and University of California at Berkeley indicates that as few as eight registers are enough for most procedures and can provide over 80 percent of the benefits. The key to the RISC concept, therefore, is the reduced size of the instruction set, not the use of multiple register sets. In this thesis, the RISC architecture from the viewpoint of design, implementation, optimizing compilers and performance has been examined. In the second chapter, the difficulties in design and creating the CISC style machine has been described. Also, the difficulties in CISC from the viewpoint of optimizing compilers has been introduced. The design philosophy and the definition of RISC architecture has been given in the third chapter. Also, the instruction set, pipeline and the aim in using large register file has been investigated. In the fourth chapter, determination of the most appropriate size of register window has been investigated. Three different multiple-register window schemes has been analyzed and compared with each other. The following characteristics of the register file has been considered in this comparisons: 1-The size of the register file and its impact on the cycle time. 2-The overhead in the execution time due to the application of a multiple - register window sheme and its impact on the absolute speed. 3-The number of transistors needed for each multiple register window scheme, and the ratio between the register area and the total chip area. As a result it was found out that two-size register window scheme is the best way to organize RISC window registers. In the fifth chapter, several strategies for managing register files in RISC has been investigated. The cost of practical strategies has been compared with a lower bound on this management overhead, obtained froma theoretical `optimal strategy` for several register files size. While the results concern specifically the RISC processor built at University of California, Berkeley, they are generally applicable to other processors with multiple register banks. In the sixth chapter, the firist two VLSI RISC processors - RISC I and RISC II - has been introduced. Also, the performance and code size of RISC I has been compared with the performance and code size of some popular CISC machines. In the seventh chapter, the MIPS-X microprocessor has been examined. This processor reduces instruction bandwidh by a factor of 6 and total memory bandwidh by a factor of 2,5 by using 2Kbyte on chip instruction cache. In the last chapter, the general-purpose, high - performance Am 29000 processor has been introduced as an example of todays comercialy avail ible RISC type processors. (xiD