M-pick fixed-priority selection and muxing

Abstract

Bu tezde, coklu(m)-secim sabit-oncelikli is duzenleyici (FPA) ve coklayc (muxing)icin bir mantk mimarisi snf onermekteyiz. Bir coklu secim FPA, n adet talep girdisindenen yuksek m tanesini oncelik srasna gore secer. _ Is duzenleyiciler genelliklecoklayclar (muxes) yonlendirir. FPA'ler ve coklayc agaclar (mux trees) gecikmeoptimizasyonu calsmalar literaturde genellikle ayr olarak ele alnmstr. Bununlabirlikte, dairesel veri bagmllklar olan baz uygulamalarda, optimize edilmesi gerekenis duzenleyici ve coklaycnn gecikmesi bir araya getirilmistir. Bunlarn dsnda, ckticin gittikce artan bir ihtiyac vardr. Bu, ornegin m > 1 oldugu zaman, her dongudem adet talebi secen ve coklayan ag anahtarlarn gerektirir. Bu tez, sabit onceligedayanan tekli secim ve coklama ile baslar ve sonra coklu (m) secim icin genellestirir./Snrlanms Toplayc` olarak adlandrdgmz bir mantk olusturma blogu, 1-secimve 2-secimli mimarileri basit problemler haline getirerek genellemede onemli bir roloynamaktadr. onerilen mimarileri, verilog ag listeleri olusturan Perl programlarvastasyla uyguladk ve bunlar ARM-artisan TSMC 180 nm en kotu durum standarthucre kutuphanesi ile Synopsys Design Compiler kullanarak sentezledik. Eldeettigimiz sonuclar vastasyla, coklu (m) secim FPA ve coklayc dizaynndaki degistokus dengesi tahlillerini gosterdik.

In this thesis, we propose a class of logic architectures for multi-pick (m-pick) fixed-priority arbitration (FPA) and muxing. An m-pick FPA selects the m topmost requests out of n inputs with priority order. Arbiters usually drive multiplexers (muxes). Latency optimization of FPAs and mux trees have usually been handled separately in the literature. However, in some applications with circular data dependencies, it is the combined latency of the arbiter and muxing that needs to be optimized. Moreover, there is an ever growing need for throughput. This requires, for example, network switches that pick and mux m requests per cycle, where m > 1. This thesis starts with 1-pick priority based selection and muxing and then generalizes it to m-pick. A logic building block that we call /Saturated Adder` plays a key role in this generalization, which makes the 1-pick and 2-pick architectures simply special cases. We have implemented the proposed architectures through Perl programs generating Verilog netlists and synthesized them using Synopsys Design Compiler with ARMArtisan TSMC 180 nm worst case standard-cell library. Through the results we have obtained, we demonstrated the trade-offs in the design of m-pick FPA and muxing.